This power reduction is made possible by a sophisticated power architecture whose verification, especially debug, poses a significant challenge given the disjoint nature of the implementation - design specification written in RTL and power architecture specified via UPF. Even high end servers compete on low power consumption and cooling costs. Web event: Catch low-power simulation bugs earlier and faster with Verdi Power-Aware DebugĮach new generation of consumer electronics devices is expected to have longer battery life than the previous one. Synopsys Power Verification & Analysis Webinar Series – 4 part series Event Registration (EVENT: 1234795 - SESSION: 1)Ĭatch low-power simulation bugs earlier and faster with Verdi Power-Aware Debug
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